vhdl計數器的編譯

① 用VHDL語言編寫可逆向計數的計數器，要求如下：

已經模擬過，請放心使用！

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity Ctl_CNT is
port (
clk: in STD_LOGIC;
back: in STD_LOGIC;

clr: in STD_LOGIC;
rst: in STD_LOGIC;
dis_h: out STD_LOGIC_VECTOR (6 downto 0);
dis_l: out STD_LOGIC_VECTOR (6 downto 0)
);

end Ctl_CNT;

architecture Ctl_CNT_arch of Ctl_CNT is
signal qh:std_logic_vector(3 downto 0);
signal ql: std_logic_vector(3 downto 0);
begin
p1: process(back,rst,clr,clk)
begin
if clr'event and clr='1' then
qh<="0000";
ql<="0000";
elsif
rst'event and rst='1' then
qh<="0110";
ql<="0110";
elsif
clk'event and clk='1'then
if back'event and back='1' then
if ql="0000" then
if qh="0000"
then ql<="1001" ;qh<="1001";
else
qh<=qh-'1';
end if;
else
ql<=ql-'1' ;
end if ;
else

if ql="1001" then
if qh="1001"
then ql<="0000" ;qh<="0000";
else
qh<=qh+'1';
end if;
else
ql<=ql+'1';
end if ;
end if;
end if;
end process p1;
p2:process(qh,ql)
begin
case qh is
when"0000"=> dis_h<="0111111";
when"0001"=> dis_h<="0000110";
when"0010"=> dis_h<="1011011";
when"0011"=> dis_h<="1001111";
when"0100"=> dis_h<="1100110";
when"0101"=> dis_h<="1101101";
when"0110"=> dis_h<="1111101";
when"0111"=> dis_h<="0000111";
when"1000"=>dis_h<="1111111";
when"1001"=> dis_h<="1101111";
when others=>dis_h<="0000000";
end case;

case ql is
when"0000"=> dis_l<="0111111";
when"0001"=> dis_l<="0000110";
when"0010"=> dis_l<="1011011";
when"0011"=> dis_l<="1001111";
when"0100"=> dis_l<="1100110";
when"0101"=> dis_l<="1101101";
when"0110"=> dis_l<="1111101";
when"0111"=>dis_l<="0000111";
when"1000"=> dis_l<="1111111";
when"1001"=> dis_l<="1101111";
when others=> dis_l<="0000000";
end case;
end process p2;
end Ctl_CNT_arch;