dsp多核編程

㈠ 璇烽棶FPGA涓嶥SP鏈変粈涔堝尯鍒錛

FPGA涓嶥SP鐨勫尯鍒濡備笅錛

1銆佺‖浠跺眰闈㈢殑涓嶅悓銆

鍦ㄧ‖浠跺眰闈錛孌SP鏄疉SIC錛屽傚悓CPU GPU涓鏍鳳紝閫傚疁浜庨噺浜ч檷浣庢垚鏈錛岀己鐐規槸錛堢‖浠訛級璁捐′竴鏃︾『瀹氾紝渚誇笉鏄撲簬淇鏀廣傝孎PGA杈冪伒媧伙紝鍙浠ラ氳繃紜浠舵弿榪拌璦榪涜屽揩閫熻捐″拰鏀硅繘錛屼絾鎴愭湰杈冮珮錛屼紶緇熶笂璁茬敤浜嶢SIC鐨刾rototype璁捐°

2銆佽蔣浠跺眰闈㈢殑涓嶅悓銆

鍦ㄨ蔣浠跺眰闈涓婏紝緇橠SP鍐欑▼搴忓拰緇欏氭牳CPU鍐欑▼搴忥紝緇橤PU鍐欑▼搴忥紝娌℃湁澶澶у尯鍒錛孌SP鏈夊畬鍠勭殑C璇璦緙栬瘧鍣ㄣ傜洰鍓嶉珮絝鐨凢PGA涓閮介泦鎴愪簡紜鏍窪SP銆

3銆佺紪紼嬭璦涓嶅悓銆

FPGA涓昏佷嬌鐢℉DL錛屽寘鎷琕HDl錛孷erilog錛岃繕鏈夋暟妯℃販鍚堢殑鎻忚堪璇璦Verilog錛岮MS絳夈侱SP浣跨敤C錛屾眹緙栬璦緙栫▼銆

4銆鍔熻兘瑙掑害涓嶅悓銆

FPGA鏅閬嶇敤浜庡疄鐜版暟瀛楃數璺妯″潡錛屽熀鏈涓婅兘瀹炵幇鎵鏈夌殑鏁板瓧鐢佃礬錛屼紶緇熺殑鏁板瓧鍔熻兘妯″潡錛屼互鍙婂㈡埛浜у搧鐗瑰畾闇奼傜殑鏁板瓧澶勭悊妯″潡銆侳PGA鐨処O妗ユ帴縐嶇被綣佸氾紝涓嶅悓縐嶇被鐨勭駭鍒鐨凢PGA鏀鎸佺殑IO鏍囧噯鍜屽崗璁閮戒笉灝界浉鍚岋紝浣嗘槸榪欎簺IO鐨勯┍鍔ㄨ兘鍔涙垨鏄鐢靛帇閮芥槸鍙緙栫▼閰嶇疆鐨勩